Review topics and practice problems are listed below for each exam. The practice problems ARE NOT derived from problems on the exams. They are simply intended to give you additional practice problems that complement the homework.

At a minimum, it would be a good idea to read all the problems and make sure you are comfortable solving them.

Exam 1

This exam will cover chapters 1-7 and 9. Everything in these chapters, plus the homework and lab content, is fair game.

A page of reference material (the laws and theorems of Boolean algebra) will also be included on the last page of the exam.

You may want to view the review slides from past semesters.
The homework solutions are available on Blackboard.

Review Topics:

• Equation simplification
• DeMorgan’s laws
• Logic gates (function, symbols, algabraic notation)
• Conversion to/from SOP/POS
• Reading equations from truth tables
• Logic to Boolean expression conversion
• Word problems
• Positive vs. negative logic
• Determining how many gates/inputs/transistors a boolean expression has
• Converting boolean expression to Karnaugh Map
• Minterm and maxterm equations
• Minimization using Karnaugh maps
• Minimization with don’t cares
• Determining prime implicants and essential prime implicants
• Functionally complete logic sets
• Conversion from one number base to another
• Using MUXs to implement logic
• Using ROMs to implement logic
• Codes (BCD, gray, etc.)

Exam 2

This exam will cover chapters 8, 10-14, appendix A, and appendix B, and the PLA lecture. Everything in these chapters, plus the homework and lab content, is fair game.

A page of reference material will also be included on the last page of the exam.

You may want to view the review slides from past semesters.
The homework solutions are available on Blackboard.

Review Topics:

• Two's compliment arithmetic and circuits
• Combinatorial timing analysis
• Timing diagrams
• False outputs and hazard free logic minimization design
• Using PLAs to implement logic
• Operation of the various latches and flip flops
• Internal structure of the various latches and flip flops
• Flip flop timing (i.e., clk-to-q time, setup time, and hold time as well as how to determine these times form a schematic drawing).
• Rising and falling edge triggered flip-flops (how they work, how they're made, and their timing characteristics)
• Registers (shift, counting, etc.)
• Counters (designing, understanding, deriving next state logic)
• Implementing counters using D, T, and JK flip flops
• Counters with additional inputs/outputs
• Counter timing diagrams
• Determining state machine behavior from schematics
• Moore vs. Mealy outputs
• Minimum period and maximum frequency for a sequential circuit
• Verilog operators - Make sure you review the concatenation, replication, and reduction operators, which don't exist in C.  You don't need to memorize precedence, but you should know how all the operators in Figure B.2 of your book work.
• Structural Verilog code
• Dataflow Verilog code
• Behavioral Verilog code (i.e., how to design a flip flop)

Exam 3

This exam will cover chapters 15-18, as well as the cascadable counters, the LC-3, and the UART lectures. Everything in these chapters/lectures, plus the homework and lab content, is fair game.

Some reference material will be included on the last pages of the exam.

You may want to view the review slides from past semesters.
The homework solutions are available on Blackboard.

Review Topics:

• State graphs
• Complete and conflict free state issues
• Creating transition tables from state graphs
• Deriving next state equations and output equations from state graphs
• Moore vs. Mealy outputs in state graphs
• Asynchronous inputs
• Metastability problem and solutions
• Sequence detectors
• One-hot encoding
• Cascaded counters
• LC-3 instructions and control (see the reference material page so you know what you do not need to memorize)
• UARTs

Final Exam

The final exam is comprehensive. It covers all reading and lecture topics (i.e., all chapters and appendices in the text, plus the PLA, cascaded counter, LC-3, UART, microsequencer, multiplier, and silicon lectures). Everything in these chapters and lectures, plus the homework and lab content, is fair game.

Some reference material will be included on the last page of the exam.

Take a look at the review slides from the last day of class.
You may also want to view the review slides from past semesters.
The homework solutions are available on Blackboard.

Review Topics:

• Boolean equation simplification
• Equivalent gates
• Digital building blocks: gates (and, or, not, nand, nor, xor, xnor), multiplexers, decoders, registers (loadable, shift, custom, etc.)
• Transition tables and excitation tables
• State machines (FSM)
• Operation and internal structure of the various flip flops
• Flip flops with additional control inputs (e.g., set, reset, enable, etc.)
• Mealy vs. Moore state machines
• Complete and conflict-free state issues
• Codes and encodings
• Functional completeness
• Cascaded counters
• ROMs
• FPGA architecture
• Verilog and HDLs
• Conversion from one number base to another
• Conversion to/from SOP/POS
• Minterms and maxterms, minterm and maxterm expansions
• Logic minimization using Karnaugh maps
• Using MUXs to implement logic
• Identifying prime implicants and essential prime implicants
• Timing analysis and diagrams
• Hazard free logic design
• LC-3 control state machine, data-path, and instructions
• Logic gates built from FETs, operation of N and P type FETs
• Flip-flop timing (e.g., setup, hold, clk-q)
• Determining state sequences from schematics
• State machines and state diagrams
• UART uses and operation