| Date | Day | Class No. |
Title | Reading Chapters |
Lecture Notes |
HW | Lab | Exam |
| 8/31 | Mon | 1 | Introduction to Digital Systems | 1 | INTRO INTRO2 |
No Lab | ||
| 9/2 | Wed | 2 | Boolean Algebra 1 | 3 | BA1 | |||
| 9/4 | Fri | 3 | Gates 1 | 4 | GATES1 | HW #1 | ||
| 9/7 | Mon | HOLIDAY | Intro to Lab |
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| 9/9 | Wed | 4 | Boolean Algebra 2 | 5 | BA2 | |||
| 9/11 | Fri | 5 | Gates 2 | 6 | GATES2 | HW #2 | ||
| 9/14 | Mon | 6 | Karnaugh Maps 1 | 7 | KM | Lab #1 | ||
| 9/16 | Wed | 7 | Karnaugh Maps 2 | 7 | KM | |||
| 9/18 | Fri | 8 | Multiplexers | 9.1-9.4 | MUX | HW #3 | ||
| 9/21 | Mon | 9 | Decoders and ROMs | 9.5-9.8 | MUX | Lab #2 | ||
| 9/23 | Wed | 10 | Number Systems | 2, 8.1-8.5 | NUMBERS | |||
| 9/25 | Fri | 11 | Arithmetic Circuits | 8.6-8.7 | ARTH | HW #4 | ||
| 9/28 | Mon | 12 | Structural Verilog | Appx. A | VERILOG1 | Lab #3 | ||
| 9/30 | Wed | 13 | Gate Delays and Timing Analysis | 10 | TANLYS | |||
| 10/2 | Fri | 14 | Programmable Logic Arrays | PLA | HW #5 | |||
| 10/5 | Mon | 15 | SR Latches and D Latches | 11.1-11.2 | LATCH | Lab #4 | ||
| 10/7 | Wed | 16 | Exam 1 Review (Optional) |
Exam 1 Lectures 1-10 |
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| 10/9 | Fri | 17 | Master/Slave Flip Flops | 11.3, 11.5-11.6 | MSFF | HW #6 | ||
| 10/12 | Mon | 18 |
Flip-Flop Timing Analysis
and Synchronous Timing | 11.4 | MSFF | Lab #5 | ||
| 10/14 | Wed | 19 | Registers and Register Files | 12 | REGISTERS | |||
| 10/16 | Fri | 20 | Dataflow Verilog | Appx. B | VERILOG2 | HW #7 | ||
| 10/19 | Mon | 21 | Counters | 13 | COUNTERS | Lab #6 | ||
| 10/21 | Wed | 22 |
Counters with Inputs,
Mealy/Moore Machines | 14 | COUNTERSI | |||
| 10/23 | Fri | 23 | State Graphs | 15 | STATEGRAPHS | HW #8 | ||
| 10/26 | Mon | 24 | Finite State Machines | 16 | FSM | Lab #7 | ||
| 10/28 | Wed | 25 | One-Hot State Machine Encoding | 17 | ONEHOT | |||
| 10/30 | Fri | 26 | Cascaded Counters | CASCNT | HW #9 | |||
| 11/2 | Mon | 27 | Exam 2 Review (Optional) | Lab #8 | ||||
| 11/4 | Wed | 28 | LC-3 Review | 124 Text Ch. 5 | LC3-1 |
Exam #2 Lectures 11-22 |
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| 11/6 | Fri | 29 | LC-3 Architecture | 124 Text Ch. 5 | LC3-1 | HW #10 | ||
| 11/9 | Mon | 30 | LC-3 Datapath | 124 Text Ch. 5 | LC3-2 | Lab #9 | ||
| 11/11 | Wed | 31 | Asynchronous Inputs | 18 | ASYNCH | |||
| 11/13 | Fri | 32 | Design Example: UART | UART | HW #11 | |||
| 11/16 | Mon | 33 | LC-3 Control |
124 Text Appendix A |
LC3-3 LC3-DC |
Lab #10 | ||
| 11/18 | Wed | 34 | Microsequencers | uSEQ | ||||
| 11/20 | Fri | 35 | FPGAs | 19 | FPGA | HW #12 | ||
| 11/23 | Mon | 36 | Exam 3 Review (Optional) | No Lab | ||||
| 11/24 | Tue | 37 | Design Example: Multiplier | MULT | ||||
| 11/25 | Wed | HOLIDAY | ||||||
| 11/27 | Fri | HOLIDAY | ||||||
| 11/30 | Mon | 38 | Design Example: Soda Machine | 20.2 | SODA | HW #13 | Lab #11 | |
| 12/2 | Wed | 39 | Design Example: Soda Machine | 20.2 | SODA |
Exam #3 Lectures 23-33 |
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| 12/4 | Fri | 40 | Design Example: Debouncer | 20.1 | DEBOUNCE | |||
| 12/7 | Mon | 41 | Silicon Design | SILICON | Lab #12 | |||
| 12/9 | Wed | 42 | Review | |||||
| 12/11 | Fri | Reading Day | ||||||
| 12/12 | Sat | Reading Day | ||||||
| 12/14 | Mon | Finals |
Final Exam Comprehensive In the Testing Center |
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| 12/15 | Tue | Finals | ||||||
| 12/16 | Wed | Finals | ||||||
| 12/17 | Thu | Finals | ||||||
| 12/18 | Fri | Finals |