ECEn 451: Introduction to Digital VLSI Circuits

Winter 2009
Instructor: David A. Penry

This schedule is subject to change

(Click to see homework and lab assignments.)
Monday
Tuesday
Wednesday
Thursday
Friday
Jan 5: First class Jan 6 Jan 7 Jan 8 Jan 9: HW 1
Jan 12: HW 2 Jan 13 Jan 14 Jan 15: Lab 1 Jan 16: NO CLASS
Jan 19: Holiday Jan 20 Jan 21: HW 3 Jan 22 Jan 23: Lab 2
Jan 26 Jan 27 Jan 28: HW 4 Jan 29 Jan 30
Feb 2: HW 5 Feb 3 Feb 4 Feb 5 Feb 6: HW 6
Feb 9 Feb 10 Feb 11 Feb 12: Lab 3 Feb 13: HW 7
Feb 16: Holiday Feb 17 (M class): Midterm 1 Feb 18: Midterm 1 Feb 19: Midterm 1 Feb 20
Feb 23: HW 8 Feb 24 Feb 25 Feb 26 Feb 27: HW 9
Mar 2: HW 10 Mar 3 Mar 4 Mar 5 Mar 6: HW 11
Mar 9 Mar 10 Mar 11: Lab 4 Mar 12 Mar 13
Mar 16: HW 12 Mar 17 Mar 18 Mar 19 Mar 20: Lab 5
Mar 23: Midterm 2 Mar 24: Midterm 2 Mar 25: Midterm 2 Mar 26 Mar 27:HW 13
Mar 30 Mar 31 Apr 1 Apr 2 Apr 3: Lab 6
Apr 6 Apr 7 Apr 8: HW 14 Apr 9 Apr 10
Apr 13: Lab 7 / Last class Apr 14 Apr 15: Reading day Apr 16: Reading day Apr 17: Finals
Apr 20: Finals Apr 21: Finals Apr 22: Finals Apr 23: Graduation Apr 24: Graduation

Reading and Lecture Schedule

 You are expected to read the assigned sections before the class in which they are discussed.
 
 
 
 Date 
Topic 
Reading 
Mon Jan 5 Course introduction, static CMOS gates —
Wed Jan 7 Static CMOS gates 1.1 - 1.4.5
Thu Jan 8 Recitation: Cadence setup and schematic editor —
Fri Jan 9 Fabrication 1.5.1 - 1.5.2, 3.2

Mon Jan 12 Standard cells, Stick diagrams 1.5.3 - 1.5.5
Wed Jan 14 Size estimation; design rules 3.3, 3.5, 8.8
Thu Jan 15 Recitation: Cadence layout —
Fri Jan 16 No class —

Mon Jan 19 Holiday: No class —
Wed Jan 21 Design flows and economics 1.6, 8.1, 8.3-8.5, 8.11
Thu Jan 22 Recitation: Lab help session —
Fri Jan 23 Voltage model and pass transistors 1.4.6 - 1.4.8

Mon Jan 26 CMOS device characteristics 2.1 - 2.2
Wed Jan 28 DC transfer 2.5
Thu Jan 29 Recitation: TBD —
Fri Jan 30 RC delay models 2.6, 4.1 - 4.2.2

Mon Feb 2 RC delay models, continued —
Wed Feb 4 Characterization 5.4 - 5.5
Thu Feb 5 Recitation: Cadence simulation tools —
Fri Feb 6 Logical effort: motivation and derivation 4.2.3 - 4.2.4, 4.3

Mon Feb 9 Logical effort: derivation and size optimization —
Wed Feb 11 Logical effort: path optimization 4.7, 5.4 - 5.5
Thu Feb 12 Recitation: midterm review —
Fri Feb 13 Logical effort: problems &mdash

Mon Feb 16 Holiday: No class —
Tue Feb 17 Static CMOS variants 6.2.1, 6.2.2, 6.2.5
Wed Feb 18 Static CMOS variants: problems and comparisons —
Thu Feb 19 Recitation: TBD —
Fri Feb 20 Pseudo-NMOS/Dynamic CMOS 6.2.3 - 6.2.4

Mon Feb 23 Dynamic CMOS —
Wed Feb 25 Domino logic —
Thu Feb 26 Recitation: TBD —
Fri Feb 27 Wire delays 4.5

Mon Mar 2 Wire engineering 4.6
Wed Mar 4 Noise 5.6
Thu Mar 5 Recitation: Cadence noise analysis tools —
Fri Mar 6 Scaling and MOS device model limitations 4.9

Mon Mar 9 Sequential element design 7.3
Wed Mar 11 Sequential element characterization and metastability 7.4.4, 7.6
Thu Mar 12 Recitation: Simulation for sequential element characterization —
Fri Mar 13 Sequential circuit timing 7.1 - 7.2

Mon Mar 16 Sequential circuit timing, cont. —
Wed Mar 18 Sequential circuit timing, cont. —
Thu Mar 19 Recitation: Midterm review —
Fri Mar 20 Sequential circuit timing, cont. —

Mon Mar 23 Array design and memory cells 11.2
Wed Mar 25 Power dissipation 4.4, 6.5
Thu Mar 26 Recitation: TBD —
Fri Mar 27 Power distribution 12.3

Mon Mar 30 Class cancelled due to illness —
Wed Apr 1 Clock distribution 12.5
Thu Apr 2 Recitation: lab hours —
Fri Apr 3 Floorplanning / P&R 1.10

Mon Apr 6 I/O and packaging 12.2, 12.4
Wed Apr 8 Verification and Test Concepts 9.2 - 9.4
Thu Apr 9 Recitation: TBD —
Fri Apr 10 Design for Test 9.5 - 9.7

Mon Apr 13 Review —