ECEn 451 Exams
Fall 2009

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Exam		Scheduled Date		Covers
Midterm #1		Feb 17 - 19 in testing center		Up to characterization
Midterm #2		Mar 23 - 25 in testing center		Logical effort to sequential element design
Final		Apr 17 - 22 in testing center		comprehensive

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Midterm 1 Topics

• What are the Cadence tools you have used so far and what are they used for?
• What do each of the masks in the AMI12 process actually control or pattern?
• What kinds of design rules are there?
• What is the purpose of design rules?
• Why are the wells attached to Vdd or GND?
• How are transistors and their sizes indicated in the layout?
• Pass transistors
• How to create a stick diagram
• How to recognize boolean expressions which can be implemented as a single static CMOS gate.
• How to determine the boolean expression which a CMOS circuit implements
• How to form conduction complements.
• DC characteristics of inverters and similar circuits
• Using the 1st order transistor model
• Shared vs. unshared diffusion and the effects on parasitic capacitance
• Propagation delays through gates, Elmore delay model
• Gate characterization

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Midterm 2 Topics

• Design costs and economics
• Computing the logical effort of a gate
• Computing the delay of a path using logical effort
• Optimizing the delay of a path using logical effort to determine the gate sizes
• Determining the optimal number of stages for a path using logical effort
• Asymmetric, Skewed, Pseduo-NMOS gates
• Dynamic gates and domino logic
• Designing latches and flops
• Determining resistance of a wire
• Using pi-models to compute wire delays
• Effects of coupling on delay
• Noise
• Metastability